Ramp and pedestal triggering is a modified version of ramp triggering. In this firing circuit, two thyristors T₁ and T₂ are connected in an anti-parallel manner for controlling the firing angle and thereby controlling the output power. The below shows the circuit configuration for ramp and pedestal triggering.

In the circuit shown above,

• D₁, D₂, D₃ and D₄ = Diodes form full-wave bridge
• V_ps = Pedestal voltage
• V_s = Source voltage
• V_C = Capacitor voltage
• V_z = Voltage across zener diode.
• T₁, T₁ = Thyristors.

In this firing circuit, variable resistor R₂ is used to control the pedestal voltage V_ps, R₂ acts as the potential divider. By adjusting the potentiometer R₂, such that V_ps is less than the threshold value of UJT (i.e., ηV_z), the capacitor then starts charging through R_V. When the capacitor voltage V_C equals threshold voltage UJT is turned ON and pulse voltage is given to thyristors T₁ and T₂.

• SCR T₁, which is in the forward-biased state is turned-ON in the interval 0 to π. After SCR T₁ is turned-ON, V_C reduces to V_ps and then to zero at ωt = π.
• SCR T₂ is forward biased and is turned-ON at ωt = π. So, T₁ is turned-ON from ωt = 0 to ωt = π and SCR T₂, is turned-ON from ωt = π to ωt = 2π. Hence, an alternating load voltage is produced as shown in the below waveforms.

Charging of capacitor is done through R_v and diode D. If the value of V_ps is less, then capacitor takes more time to reach threshold voltage and hence the firing angle delay occurs which makes output voltage less. Hence, it can be concluded that output voltage is directly proportional to V_ps.

Time taken for the capacitor to charge from V_ps to ηV_z, can be derived as follows,

In the above equation RC is the time constant. From the above equation, we have,

Where ω is the input frequency and η is the intrinsic stand-off ratio of UJT.