Ramp and pedestal triggering is a modified version of ramp triggering. In this firing circuit, two thyristors T_{1} and T_{2} are connected in an anti-parallel manner for controlling the firing angle and thereby controlling the output power. The below shows the circuit configuration for ramp and pedestal triggering.

#### In the circuit shown above,

- D
_{1}, D_{2}, D_{3}and D_{4}= Diodes form full-wave bridge - V
_{ps}= Pedestal voltage - V
_{s}= Source voltage - V
_{C}= Capacitor voltage - V
_{z}= Voltage across zener diode. - T
_{1}, T_{1}= Thyristors.

In this firing circuit, variable resistor R_{2} is used to control the pedestal voltage V_{ps}, R_{2} acts as the potential divider. By adjusting the potentiometer R_{2}, such that V_{ps} is less than the threshold value of UJT (i.e., Î·V_{z}), the capacitor then starts charging through R_{V}. When the capacitor voltage V_{C} equals threshold voltage UJT is turned ON and pulse voltage is given to thyristors T_{1} and T_{2}.

- SCR T
_{1}, which is in the forward-biased state is turned-ON in the interval 0 to Ï€. After SCR T_{1} is turned-ON, V_{C} reduces to V_{ps} and then to zero at Ï‰t = Ï€. - SCR T
_{2} is forward biased and is turned-ON at Ï‰t = Ï€. So, T_{1} is turned-ON from Ï‰t = 0 to Ï‰t = Ï€ and SCR T_{2}, is turned-ON from Ï‰t = Ï€ to Ï‰t = 2Ï€. Hence, an alternating load voltage is produced as shown in the below waveforms.

_{1}, which is in the forward-biased state is turned-ON in the interval 0 to Ï€. After SCR T_{1}is turned-ON, V_{C}reduces to V_{ps}and then to zero at Ï‰t = Ï€._{2}is forward biased and is turned-ON at Ï‰t = Ï€. So, T_{1}is turned-ON from Ï‰t = 0 to Ï‰t = Ï€ and SCR T_{2}, is turned-ON from Ï‰t = Ï€ to Ï‰t = 2Ï€. Hence, an alternating load voltage is produced as shown in the below waveforms.Charging of capacitor is done through R_{v} and diode D. If the value of V_{ps} is less, then capacitor takes more time to reach threshold voltage and hence the firing angle delay occurs which makes output voltage less. Hence, it can be concluded that output voltage is directly proportional to V_{ps}.

#### Time taken for the capacitor to charge from V_{ps} to Î·V_{z}, can be derived as follows,

In the above equation RC is the time constant. From the above equation, we have,

Where Ï‰ is the input frequency and Î· is the intrinsic stand-off ratio of UJT.