Architecture of 8086 Microprocessor – Block Diagram & its Parts

The 8086 is a 16-bit microprocessor with a 16-bit internal and external data bus. With 20 address lines, it can access upto 220 = 1 MB of memory. The functional diagram of the 8086 microprocessor is shown in the below figure. The architecture of the 8086 microprocessor consists of two independent sections or units, the Bus Interface Unit (BIU) and Execution Unit (EU).

Architecture of 8086 Microprocessor

Bus Interface Unit (BIU) :

The bus interface unit interfaces 8086 with the external world. It handles all the data transfer functions. The BIU performs read and write operations on data in the memory and on the external devices connected to the ports of the microprocessor, and it also sends out addresses. That means all external operations are performed by BIU. To perform these operations BIU contains some functional parts, they are,

Instruction Queue :

The instruction queue holds the six bytes of instruction fetched from the code memory by the BIU that are to be executed by the EU. The instruction queue contains registers that work on FIFO (first-in-first-out) principle. Since EU and BIU are independent, whenever the execution unit starts decoding and executing fetched instructions, the BIU fetches additional instructions to the queue from the code memory for execution.

Again when the execution unit starts executing fetched instructions in the queue, again the BIU will add instructions to the queue at the same time. Since the fetching of instructions from the memory and execution of instructions in the queue are done as the same time, both the operations will overlap. This is called Pipelining which speeds up the execution by reducing CPU waiting state time as illustrated in the below figure.

Architecture of 8086 Microprocessor

Segment Registers :

The 8086 microprocessor has 1 MegaByte (220 bits = 1 Mb) of segmentized memory divided into 16 logical segments. The maximum size of each segment is 64kb so that any location within the segment can be accessed with a 16-bit logical address. At any given time, 8086 works with only four 64kb segments which are independent and separately addressable units. Each segment is associated with segment registers that are 16 bits wide. The four registers related to four segments are,

  • Data Segment Register (DS) – It is used to point to the base address of the data register.
  • Code Segment Register (CS) – It is used to point to the base address of the code register.
  • Extra Segment Register (ES) – It holds the base address of the extra memory segment.
  • Stack Segment Register (SS) – It holds the base address of the stack memory segment.

Instruction Pointer (IP) :

The instruction pointer is similar to the program counter in 8085 CPU. The IP is updated by BIU so that it contains the offset (distance in byte from base address) of the next instruction. That is IP points to the next instruction to be fetched from the code segment.

Execution Unit (EU) :

The execution unit tells the bus interface unit where to fetch instruction or data from. It decodes the instruction and performs arithmetic and logical operations using the ALU. This execution unit provides effective addresses of memory locations. Then, this address is added to the base address provided by segment registers in the bus interface unit. The execution unit consists of the following parts,

  • Control System – It manages all the operations in the execution unit.
  • Instruction Decoder – It translates or decodes the instructions in the queue for execution.
  • Arithmetic and Logic Unit – Depending upon the given instructions the ALU performs operations like addition, subtraction, AND, OR, NOT, shifting of binary numbers, etc, on the data.
  • Flag Register – It is a 16-bit register with 16 flip-flops or flags. Out of 16 flags, only 9 are used. In these 9 flags, six flags are used for indicating the status of the result of an operation, and three flags are used to control certain operations in the EU.
  • General Purpose Registers – The 8086 contains four 16-bit general-purpose registers (AX, BX, CX, and DX) used to store data, variables, temporary results and can be used as counters. Each register is divided into two 8-bit registers i.e., AX as AH and AL, BX as BH and BL, CX as CH and CL, and DX as DH and DL.
  • Stack Pointer (SP) – It is a 16-bit register that contains the offset from the start of the stack segment to the stack top.
  • Pointer and Index Registers (BP, SI, and DI) – These registers are also 16-bit wide used as a pointer to a memory location in one of the segments.

Since, the two operations i.e., fetching an instruction from code memory by bus interface unit and execution of the instruction by execution unit are performed simultaneously, it is called parallel processing.

The A-Bus, B-Bus, and C-Bus are the internal buses of the 8086 processor. It is known that the BIU is responsible for the transfer of instructions, addresses, and data on the system bus to the execution unit, it performs these functions through C-Bus. The B-bus is used to perform instruction fetch, data fetch, address transfer, and computations of the effective address of the memory and the A-Bus is an interface between BIU and EU.

Why 8086 Internal Architecture is Divided into EU and BIU?

In general, almost all early 8-bit CPUs used the approach of “fetch-fetch-fetch-execute-fetch-fetch-fetch-fetch” while running a program from code memory. During the time that instruction is fetched, the CPU will be in the waiting state. In order to eliminate this CPU waiting state and to increase the execution speed, the 8086 processor is composed of two sections or units that operate asynchronously.

So there are two independent units i.e., BIU and EU, in the 8086 microprocessor. The BIU fetches instructions from code memory whenever the memory is free. The BIU gets instructions bytes and shifts them into the internal memory called instruction queue or pipeline. The EU gets the instructions out of the queue and executes them as fast as it can.

The BIU puts instructions in one end of the pipeline and the EU takes them out at the other end of the pipeline. Thus, BIU-EU combination can fetch and execute code simultaneously. Hence, to increase the execution speed of the processor, 8086 architecture is divided into BIU and EU.

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